1. Field
Embodiments of the inventive concept relate to a memory system, and more particularly, to a memory system employing cyclic redundancy check (CRC).
2. Description of Related Art
As the operating speeds of memory systems have increased, a probability of an error occurring during data transmission between a memory device and a memory controller constituting a memory system has also increased. Thus, when data transmission is performed between a memory device and a memory controller in recent memory systems, a specific code corresponding to data is generated and transmitted together with the data. And, the recent memory systems are gradually employing a CRC technique of analyzing the specific code applied together with data to correct a bit error that may occur in the data. The specific code generated to correspond to data to be transmitted is referred to as error check code (ECC). Apparatuses employing CRC transmit an ECC together with data, and analyze an ECC received together with data. When it is determined that a bit error is detected from the received data, the apparatuses request retransmission of the data, from which the error is detected, to correct the error. When the bit error rate (BER) of the data is high in this process, the retransmission request may be repeated for error correction. In particular, when the BER exceeds an error correction capability of a memory system, the system continuously repeats only a retransmission request, which results in a system hang.